1. Field of the Invention
The subject of the present invention is a transistor structure with high input impedance and high current capability.
Such structure can be used, for example, as a selection transistor for a phase change memory cell comprising, in addition to the selection transistor, also a phase change storage element.
2. Description of the Related Art
As is known, phase change storage elements comprise storage elements made of a class of materials having the unique property of switching in a reversible way between two phases having distinct and measurable electrical characteristics, associated to each phase. For example, these materials can switch between a disorderly amorphous phase and an orderly crystalline or polycrystalline phase. In addition, these materials can assume a plurality of states, comprised between the amorphous state and the polycrystalline state, each associated to different electrical characteristics (typically, different electrical resistances).
The materials that can advantageously be used in phase change cells are alloys of elements of group VI of the periodic table, such as Te or Se, referred to also as calcogenides or calcogenic materials. Hence, hereinafter, the term “calcogenic material” is used to designate all the materials that can be switched between at least two different phases in which they have different electrical properties (resistances) and consequently include the elements of group VI of the periodic table and their alloys.
The currently most promising calcogenide is formed by an alloy of Ge, Sb and Te (Ge2Sb2Te5), which is already widely used for storing information in overwritable disks.
The use of phase change storage elements has been already proposed in memory arrays formed by a plurality of memory cells arranged in rows and columns. In order to prevent the memory cells from being disturbed by the noise caused by adjacent memory cells, in general each memory cell comprises a phase change storage element and a selection element, such as a MOS transistor, a bipolar transistor, or a diode.
For example, FIG. 1 shows a memory array 1 formed by a plurality of memory cells 2 arranged in rows and columns and connected to bitlines 3 (parallel to the columns of the memory array 1) and wordlines 4 (parallel to the rows of the memory array 1). Each memory cell 2 comprises a calcogenic memory element 6 and a selector element 5, here formed by a MOS transistor. Each selector element 5 has its gate region connected to the respective wordline 4, its source region connected to ground, and its drain region connected to a terminal of the calcogenic memory element 6. Each calcogenic memory element 6 is connected between the respective selection element and the respective bitline 3.
In the memory array 1, in particular operating conditions, for example during the programming step, the bitlines 3 drain high currents. The ability to drain such high currents can be met using, as selection element, a bipolar transistor with a large area. On the other hand, for optimal operation, the selection transistor should present a high input impedance, typical of MOSFETs.
This dual objective is shared also by other applications where it is desirable to have a pull-down transistor capable of driving high currents and having a high input impedance.
The need thus exists of having a transistor structure capable of combining the characteristics indicated above of bipolar and transistors MOSFETs, without requiring a large integration area.